A substrate of super junction MOSFET is constructed by repeatedly arranging a PN column pair of one kind in a transistor forming area as disclosed in, for example, JP-A-2004-146689. As its result, in comparison with a conventional MOSFET, it is possible to reduce on-resistance by a reduction in drift resistance and perform high speed switching.
Although the high speed switching can be performed, an electric current between a drain and a source is suddenly interrupted at a switching time from an on-state to an off-state. Thus, the voltage between the drain and the source is greatly jumped up so that problems such as a degradation in breakdown robustness amount, radio noise generation, etc. are caused.
Further, a MOSFET having a super junction structure is disclosed in, for example, US Patent Application Publication No. 2005-0035401. The super junction structure is constructed by alternately arranging an N type impurity area and a P type impurity area constituting a PN column pair. In comparison with a conventional MOSFET, it is possible to reduce on-resistance by a reduction of drift resistance and perform high speed switching.
However, in the super junction MOSFET, the PN column pair is instantly depleted. Therefore, in comparison with the conventional MOSFET, although the high speed switching can be performed at high voltage operation, an electric current between a drain and a source is suddenly interrupted at a switching time from an on-state to an off-state. Therefore, the voltage between the drain and the source is greatly jumped up, and problems such as radio noise generation, a degradation in breakdown robustness amount, deterioration of recovery characteristics, etc. are caused.
Thus, it is required for a semiconductor device to restrain the jumping-up of the voltage at the switching time from an on-state to an off-state.